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IDT74LVC827A 3.3V CMOS 10-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 10-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O
* 0.5 MICRON CMOS Technology * ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) * VCC = 3.3V 0.3V, Normal Range * VCC = 2.7V to 3.6V, Extended Range * CMOS power levels (0.4 W typ. static) * Rail-to-rail output swing for increased noise margin * All inputs, outputs, and I/O are 5V tolerant * Supports hot insertion * Available in SOIC, SSOP, QSOP, and TSSOP packages
IDT74LVC827A
FEATURES:
DESCRIPTION:
This 10-bit buffer/driver is built using advanced CMOS technology. The LVC827A device provides a high-performance bus interface for wide data paths or buses carrying parity. The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable (OE1 or OE2) input is high, all ten outputs are in the high-impedance state. The LVC827A provides true data at its outputs. The LVC827A has been designed with a 24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V system environment.
DRIVE FEATURES:
* High Output Drivers: 24mA * Reduced system switching noise
APPLICATIONS:
* 5V and 3.3V mixed voltage systems * Data communication and telecommunication systems
FUNCTIONAL BLOCK DIAGRAM
OE1 OE2
1 13
A1
2
23
Y1
TO NINE OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
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(c) 1999 Integrated Device Technology, Inc.
OCTOBER 1999
DSC-4647/1
IDT74LVC827A 3.3V CMOS 10-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Max VTERM Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, VI < 0 or VO < 0 Continuous Current through each VCC or GND -0.5 to +6.5 -65 to +150 -50 to +50 -50 100 TSTG IOUT IIK IOK ICC ISS
Unit V C mA mA mA
OE1 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 GND
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VCC Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 OE2
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE (TA = +25C, F = 1.0MHz)
Symbol CIN COUT CI/O Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 4.5 5.5 6.5 Max. 6 8 8 Unit pF pF pF
NOTE: 1. As applicable to the device type.
SOIC/ SSOP/ QSOP/ TSSOP TOP VIEW
PIN DESCRIPTION
Pin Name OEx Ax Yx I/O I I O Description When both are LOW the outputs are enabled. When either one or both are HIGH the outputs are High Z. 10-Bit Data Inputs 10-Bit Data Outputs
FUNCTION TABLE (EACH BUFFER)(1)
Inputs OE1 L L H X OE2 L L X H Ax L H X X Outputs Yx L H Z Z 3-State Function Transparent
NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High Impedance
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IDT74LVC827A 3.3V CMOS 10-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = -40C to +85C
Symbol VIH VIL IIH IIL IOZH IOZL IOFF VIK VH ICCL ICCH ICCZ ICC High Impedance Output Current (3-State Output pins) Input/Output Power Off Leakage Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = 0V, VIN or VO 5.5V VCC = 2.3V, IIN = -18mA VCC = 3.3V VCC = 3.6V VIN = GND or VCC -- -- -- -- -- -- -- -0.7 100 -- -- -- 50 -1.2 -- 10 10 500 A V mV A VCC = 3.6V VO = 0 to 5.5V -- -- 10 A Parameter Input HIGH Voltage Level Input LOW Voltage Level Input Leakage Current VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V VI = 0 to 5.5V Test Conditions Min. 1.7 2 -- -- -- Typ.(1) -- -- -- -- -- Max. -- -- 0.7 0.8 5 A V Unit V
Quiescent Power Supply Current Variation
3.6 VIN 5.5V(2) One input at VCC - 0.6V, other inputs at VCC or GND
A
NOTES: 1. Typical values are at VCC = 3.3V, +25C ambient. 2. This applies in the disabled state only.
OUTPUT DRIVE CHARACTERISTICS
Symbol VOH Parameter Output HIGH Voltage VCC = 2.3V VCC = 2.3V VCC = 2.7V VCC = 3V VCC = 3V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3V IOH = - 24mA IOL = 0.1mA IOL = 6mA IOL = 12mA IOL = 12mA IOL = 24mA Test Conditions(1) VCC = 2.3V to 3.6V IOH = - 0.1mA IOH = - 6mA IOH = - 12mA Min. VCC - 0.2 2 1.7 2.2 2.4 2.2 -- -- -- -- -- Max. -- -- -- -- -- -- 0.2 0.4 0.7 0.4 0.55 V Unit V
NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = - 40C to + 85C.
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IDT74LVC827A 3.3V CMOS 10-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
OPERATING CHARACTERISTICS, VCC = 3.3V 0.3V, TA = 25C
Symbol CPD CPD Parameter Power Dissipation Capacitance per Buffer/Driver Outputs enabled Power Dissipation Capacitance per Buffer/Driver Outputs disabled Test Conditions CL = 0pF, f = 10Mhz Typical 24 5 Unit pF
SWITCHING CHARACTERISTICS(1)
VCC = 2.7V Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tSK(o) Parameter Propagation Delay Ax to Yx Output Enable Time OEx to Yx Output Disable Time OEx to Yx Output Skew(2) -- -- -- 1 ns -- 7.3 1.8 6.7 ns -- 8.5 1 7.3 ns Min. -- Max. 7.1 VCC = 3.3V 0.3V Min. 1 Max. 6.7 Unit ns
NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = - 40C to + 85C. 2. Skew between any two outputs of the same package and switching in the same direction.
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IDT74LVC827A 3.3V CMOS 10-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS
Symbol VLOAD VIH VT VLZ VHZ CL VCC(1)= 3.3V0.3V VCC(1)= 2.7V 6 2.7 1.5 300 300 50 6 2.7 1.5 300 300 50 VCC(2)= 2.5V0.2V 2 x Vcc Vcc Vcc / 2 150 150 30 Unit V V V mV mV pF
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
VIH VT 0V VOH VT VOL VIH VT 0V
LVC Link
VCC 500 Pulse (1, 2) Generator VIN D.U.T. RT 500 CL VOUT
VLOAD Open GND CONTROL INPUT
Propagation Delay
ENABLE DISABLE VIH VT 0V VLOAD/2 VOL+VLZ VOL VOH VOH-VHZ 0V
LVC Link
tPZL OUTPUT SWITCH NORMALLY VLOAD LOW tPZH OUTPUT SWITCH NORMALLY GND HIGH VLOAD/2 VT tPHZ VT 0V
tPLZ
LVC Link
Test Circuit for All Outputs
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate 10MHz; tF 2.5ns; tR 2.5ns. 2. Pulse Generator for All Pulses: Rate 10MHz; tF 2ns; tR 2ns.
NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Enable and Disable Times
SWITCH POSITION
Test Open Drain Disable Low Enable Low Disable High Enable High All Other Tests Switch VLOAD GND Open
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL VIH VT 0V VOH VT VOL VOH VT VOL
tSU
tH
tREM
tSU
tH
VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V
LVC Link
INPUT
Set-up, Hold, and Release Times
tPLH1
tPHL1
OUTPUT 1
tSK (x)
tSK (x)
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE
VT
OUTPUT 2 tPLH2 tPHL2
VT
Pulse Width
LVC Link
LVC Link
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Output Skew - tSK(X)
NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
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IDT74LVC827A 3.3V CMOS 10-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
LVC IDT XX X Temp. Range Bus-Hold XX XXXX Device Type Package
SO PY Q PG 827A Blank 74
Small Outline IC (gull wing) Shrink Small Outline Package Quarter Size Small Outline Package Thin Shrink Small Outline Package 10-Bit Buffer/Driver with 3-State Outputs, 24mA No Bus-hold -40C to +85C
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